10/20(2)

module A01_4_Unit (y_out,x_in1,x_in2,x_in3,x_in4);

input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;

reg y_out,y1,y2;

always

begin
#1 y1=x_in1&x_in2;
#1 y2=x_in3&x_in4;
#1 y1=x_in1 nor x_in2;
end

endmodule