星期一

10/20(1)

module A01_4_Unit (y_out,x_in1,x_in2,x_in3,x_in4);

input x_in1,x_in2,x_in3,x_in4;
output y_out;wire y1,y2;

and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);

endmodule

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