10/06上課練習

Design a verilog model of a half adder and erite a testbench to verify the designed verilog model .



module Add_half (sum,c_out,a,b);

input a,b;
output sum,c_out;
wire c_out_bar;

xor (sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule