11/17

module compare_2_str(a_lt_b,a_gt_b,a_eq_b,a,b);
input [1:0] a,b;
output a_lt_b,a_gt_b,a_eq_b;
reg a_lt_b,a_gt_b,a_eq_b;
always @(a or b)
begin
a_lt_b=0;
a_gt_b=0;
a_eq_b=0;
if(a==b) a_eq_b=1;
else if(a>b) a_gt_b=1;
else a_lt_b=1;
end
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2) clk=~clk;
#(PERIOD/2) clk=~clk;
end
always @(posedge clk)
if($time>1000) #(PERIOD-1) $stop;
endmodule

module test;
wire a1,a0,b1,b0;
wire a_lt_b,a_gt_b,a_eq_b;

system_clock #400 clk(a1);
system_clock #200 clk(a0);
system_clock #100 clk(b1);
system_clock #50 clk(b0);

compare_2_str A1(a_lt_b,a_gt_b,a_eq_b,a1,a0,b1,b0);
endmodule

10/20(3)

module top;
wire x_in1,x_in2,x_in3,x_in4;
wire y_out;

system_clock #200 clock1(x_in1);
system_clock #150 clock2(x_in2);
system_clock #100 clock1(x_in3);
system_clock #50 clock2(x_in4);

A01_4_Unit AH1(y_out,x_in1,x_in2,x_in3,x_in4);

endmodule


module A01_4_Unit (y_out,x_in1,x_in2,x_in3,x_in4);

input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;
and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);

endmodule

module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/4) clk = ~clk;
#(PERIOD/4) clk = ~clk;
#(PERIOD/4) clk = ~clk;
#(PERIOD/4) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

10/20(2)

module A01_4_Unit (y_out,x_in1,x_in2,x_in3,x_in4);

input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;

reg y_out,y1,y2;

always

begin
#1 y1=x_in1&x_in2;
#1 y2=x_in3&x_in4;
#1 y1=x_in1 nor x_in2;
end

endmodule

10/20(1)

module A01_4_Unit (y_out,x_in1,x_in2,x_in3,x_in4);

input x_in1,x_in2,x_in3,x_in4;
output y_out;wire y1,y2;

and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);

endmodule

10/13 Add_full

module Add_full(sum,c_out,a,b,c_in);

input a,b,c_in;
output sum_c_out;
wire w1,w2,w3;

Add_half M1(w1,w2,a,b);
Add_half M2(sum,w3,w1,c_in);
or (c_out,w2,w3);

endmodule

10/13上課練習

module top;
wire a,b;
wire sum,c_out;

system_clock #100 clock1(a);
system_clock #50 clock2(b);

Add_half AH1(sum,c_out,a,b);

endmodule

module Add_half(sum,c_out, a, b);

input a,b;
output sum,c_out;
wire c_out_bar;


xor(sum, a, b);
nand(c_out_bar, a, b);
not(c_out,c_out_bar);
endmodule


module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

10/06上課練習

Design a verilog model of a half adder and erite a testbench to verify the designed verilog model .



module Add_half (sum,c_out,a,b);

input a,b;
output sum,c_out;
wire c_out_bar;

xor (sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

9/22上課練習

module top;
wire a,b;
reg c;
system_clock #100 clock1(a);
system_clock #50 clock2(b);
always
#1 c=a&b;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
#(PERIOD-1)$stop;
endmodule

老師的BLOG

http://dyu9502.blogspot.com/